1. Field of the Invention
The present invention relates to a semiconductor memory device having stacked capacitors, and more particularly to improvements in the configuration of a stacked capacitor capable of increasing capacitance of the capacitor, and a manufacturing method thereof.
2. Description of the Background Art
Recently, semiconductor memory devices are in great demand as information processing apparatuses such as computers have come to be widely used. Semiconductor memory devices having large memory capacitances and capable of high speed operation are desired. Accordingly, the technology in association with the higher degree of integration, the high speed responsiveness and higher reliability of the semiconductor memory devices has been developed.
A DRAM (Dynamic Random Access Memory) is a semiconductor memory device capable of inputting/outputting memory data at random. Generally, a DRAM comprises a memory cell array which is a memory region storing a large number of data and peripheral circuits required for external input/output.
FIG. 16 is a block diagram showing a structure of a common DRAM. Referring to the figure, the DRAM 50 comprises a memory cell array 51 for storing data signals representing memory information, a row and column address buffer 52 for externally receiving an address signal for selecting a memory cell constituting a unit memory circuit, a row decoder 53 and a column decoder 54 for designating the memory cell by interpreting the address signal, a sense refresh amplifier 55 for amplifying the signals stored in the designated memory cell to read the same, a data in buffer 56 and a data out buffer 57 for data input/output, and a clock generator 58 for generating clock signals.
The memory cell array 51 occupying a large area on a semiconductor chip is constituted by an arrangement of a plurality of memory cells each storing unit memory data. FIG. 17 is an equivalent circuit diagram of 4 bits of memory cells constituting the memory cell array 51. The shown memory cell is a 1-transistor 1-capacitor type memory cell comprising one MOS (Metal Oxide Semiconductor) transistor and one capacitor element connected thereto. The memory cell structure of this type is simple and it enables improvement of the degree of integration of the memory cell array, so that the structure is widely used for DRAMs having large capacitances.
FIG. 18 is a plan view of the structure of the memory cell array. This figure corresponds to an equivalent circuit diagram of FIG. 17. The memory cell array comprises a plurality of word lines 27, 27 extending in a row direction, and a plurality of bit lines 42, 42 extending in a column direction. A memory cell 45 is formed in the vicinity of an intersecting portion of a word line 27 and a bit line 42.
FIG. 19 is a cross sectional view of the memory cell 45 taken along the line 19--19 of FIG. 18. The memory cell 45 comprises one access transistor 21 and one capacitor 22. The access transistor 21 comprises a gate electrode 4 formed on a main surface of a semiconductor substrate 1 through a gate insulating film 5a, and a pair of source and drain regions 6, 6 formed on the surface of the semiconductor substrate 1. The gate electrode 4 is constituted by a part of the word line 27.
That capacitor 22 comprises a lower electrode (a storage node) 7, a dielectric film 8 and an upper electrode (a cell plate) 9. A part of the lower electrode 7 is connected respectively to opposite sides of the source and drain regions 6, 6 of the access transistor 21. One end of the lower electrode 7 extends over the gate electrode 4 through an insulating film 5b. The other end of the lower electrode 7 extends on the word line 27 formed over a field oxide film 3 through the insulating film 5b.
The capacitor in which the dielectric film 8 is formed on the lower electrode 7 stacked on the surface of the semiconductor substrate 1 is called a stacked capacitor.
As described in the beginning, a memory cell structure of the DRAM is miniaturized for high integration. Accordingly, a plane area occupied by the capacitor is also reduced. A capacitance of the capacitor need to retain more than a prescribed capacitance. The capacitance of the capacitor is in proportion to the area where the dielectric film 8, the lower electrode 7 and the upper electrode 9 face one another. In the stacked capacitor 22 shown in FIG. 19, a surface region P and a side region S of the lower electrode 7 constitute a capacitance portion.
Next, a manufacturing method of the memory cell of the DRAM shown in FIG. 19 will be described. FIGS. 20A-20D are cross sectional views illustrating the manufacturing steps of the memory cell.
As shown in FIG. 20A, the field oxide film 3 consisting of an oxide film is formed on the surface of the semiconductor substrate 1. A region enclosed by the filed oxide film 3 constitutes an element forming region 2.
In FIG. 20B, a conductive film of polycrystalline silicon and the insulating film 5b of an oxide film are deposited on the gate insulating film 5a formed on the surface of the semiconductor substrate 1 and selectively etched Accordingly, the gate electrodes 4a, 4b are formed in prescribed positions, respectively. The insulating film 5b of an oxide film is then deposited. Further, the oxide film is etched to expose the surface region 2 other than the gate electrode 4a. At the same time, the insulating film 5b is left in a self aligning manner on sidewall portions of the gate electrodes 4a, 4b. The top surface portions and the side portions of the gate electrodes 4a, 4b are covered with the insulating film 5b. Moreover, impurities are injected by an ion implantation method into the surrounding surface region 2 of the gate electrode 4a so as to form an impurity diffusion layer 6 of a conductivity type opposite to that of the substrate 1.
In FIG. 20C, a conductive film 7 of polycrystalline silicon is formed which extends over the gate electrode 4a to the gate electrode 4b on the field oxide film 3 through the diffusion layer 6.
In FIG. 20D, the dielectric layer 8 formed of a multi-layer film of an oxide film and a nitride film, and the conductive film 9 of polycrystalline silicon are deposited. The capacitor 22 is formed by the manufacturing steps described above.
Generally, if an area occupied by a storage element is 1/k due to an increase in the degree of integration, a surface area of the conductive film 7 is also reduced to 1/k. However, even if the surface area is 1/k, a length around the surface is only 1/.sqroot.k. Therefore, a side area of the conductive film 7 is only reduced to 1/.sqroot.k as well if a thickness of the film is the same, so that a contribution rate of the side portion of the conductive film 7 to storage capacitance increases as the degree of integration increases. If the conductive film 7 is made thicker in order to increase the area of the side portion, the following phenomenon occurs.
The conductive film 7 is formed lying over high step portions formed by the gate electrode 4 and the like. Therefore, if the film is thick, an unnecessary portion of the conductive film 7 is liable to remain unremoved in a region 10 of the bottom portion of the steps in the process for patterning the film in a prescribed shape. This etching residue 17 is liable to occur in such places as shown in FIG. 18, and hence there is a problem that a short circuit to an adjacent pattern is liable to occur.
Furthermore, as shown in FIG. 21, if the conductive film 7 is thickly formed, the side area thereof increases, whereas the surface area decreases because the surface is smoothed. Accordingly, there is a problem that the capacitance of the capacitor decreases.